1. Field of the Invention
The present invention relates to a semiconductor device that has a clock phase adjusting circuit such as a delay locked loop (DLL) circuit. The clock phase adjusting circuit adjusts the phase of a clock supplied from an external circuit or the like and produces an internal clock that lags behind the clock by a given phase. More particularly, the present invention is concerned with a semiconductor device having an ability to fetch and output data at a given correct phase irrespective of a dispersion in the characteristics thereof, a change in ambient temperature, a fluctuation in a supply voltage, or the like. For this purpose, the semiconductor device produces an internal clock that lags behind the clock supplied from an external circuit or the like by a given phase of 90.degree. or 120.degree.. Data which is to be input to a high-speed memory or the like represented by a dynamic random access memory (hereinafter abbreviated to a DRAM) is then locked to the internal clock.
2. Description of the Related Art
Normally, a semiconductor chip constructing a semiconductor integrated circuit (LSI) inputs data that is an external input signal, carries out a processing operation in accordance with the input data, and then outputs desired data. In general, as far as a general-purpose LSI is concerned, desired data must be output stably irrespective of a dispersion in the characteristics thereof, a change in ambient temperature, a fluctuation in a supply voltage, or the like. For this purpose, it is important at what timing the external input data should be output. This makes it necessary to define the above timing at advance in the form of a specification. Typically, a DRAM will be taken as an example. A maximum frequency of an address signal as well as the timing in which data is output on the basis of a transition edge of the address signal, a data set-up time required for writing data, and the like, are defined in advance.
In recent years, the frequency of a clock employed in a central processing unit (CPU) in a computer system has become higher and various electronic circuits are operated at a higher speed. A main memory or interface in the CPU are therefore required to operate at a higher speed. Various types of novel DRAMs including a synchronous DRAM (normally abbreviated to an SDRAM) that permits a data transfer rate of, for example, 100 MHz or higher have been proposed.
In a novel DRAM, such as the SDRAM, that operates at high speed, it is necessary to output data in a given accurate phase (for example, 90.degree. or 120.degree.) relative to a clock that is input from an external circuit or the like. Normally, a DLL circuit having an ability to accurately adjust the difference between the phase of an external clock and the phase of an internal clock and produce this internal clock, is incorporated in the DRAM. Data which is to be output from the DRAM is locked to an internal clock produced by the DLL circuit, that is, a DLL clock.
However, some users use the DRAM at relatively low frequencies. In this case, a DLL clock that is a clock produced by the DLL circuit is compared in phase with a real clock that is a clock input to the DRAM. Either one of the DLL clock and the real clock whose phase is leading in comparison with the phase of the other clock is selected and used as an internal clock of a semiconductor device. It is thus avoided that clock access time elapsing from the time when a clock is input until the time when data is output unnecessarily becomes long.
Now, an explanation concerning an exemplary configuration of a conventional semiconductor device, which has an ability to compare the phase of a DLL clock with the phase of a real clock, and also an explanation concerning the operations thereof will be given with reference to FIGS. 1, 2A, and 2B. This will contribute to a better understanding of problems underlying a semiconductor device having an ability to compare the phase of one clock with the phase of another clock according to the prior art. FIGS. 1, 2A, and 2B will be described later in the "Brief Description of the Drawings" section.
The exemplary configuration of a conventional semiconductor device having an ability to compare the phase of one clock with the phase of another clock, which is shown in FIGS. 1, 2A, and 2B, has been disclosed in the specification of the prior patent application filed by the same applicant (Fujitsu Ltd.) as the present application (Japanese Patent Application No. 9-006796 filed on Jan. 17, 1997).
As shown in FIG. 1, the conventional semiconductor device having an ability to compare the phase of one clock with the phase of another clock consists of a DLL circuit 100 including a delay circuit portion (See FIG. 6) for producing a DLL clock DLLCLK by delaying an external clock EXCLK, which is input from an external circuit or the like via an input buffer 500, by a given phase; and a clock phase comparing circuit 150 for comparing the phase of the DLL clock output from the DLL circuit 100 with the phase of a real clock RECLK output from the input buffer 500.
To be more specific, an external clock serving as a reference for enabling a computer system to operate normally is adjusted (e.g., lowered) to a given level by the input buffer 500. Thereafter, the thus adjusted clock is output as a real clock that has undergone a phase delay to some extent. On the other hand, the DLL circuit 100 controls the number of delay stages in the delay circuit portion to preset the amount of delay equivalent to a phase delay of 90.degree. or of 120.degree. relative to the external clock. Furthermore, the clock phase comparing circuit 150 compares the phase of the DLL clock, which is output through the delay stages, with the phase of the real clock output directly from the input buffer 500 without passing through the DLL circuit 100. At this time, the phase of the DLL clock is compared with the phase of the real clock within the cycle of a window pulse signal Sw produced by using a division technique for a frequency of the real clock provided by a division circuit 400. Either one of the above two clocks that is relatively leading is detected as an internal clock for an output signal.
Either one of the DLL clock and the real clock, which has been detected as mentioned above, is supplied to an output buffer 600 in the semiconductor device. The data output buffer 600 fetches data DATA synchronously with either one of the DLL clock and the real clock which is supplied from the clock phase comparing circuit 150. The fetched data is then output as an output signal DOUT to the outside of the semiconductor device.
Furthermore, the way in which the clock phase comparing circuit 150 (FIG. 1) compares the phase of a DLL clock with the phase of a real clock will be described with reference to a timing chart of FIG. 2A. Assuming that a clock frequency (inverse number of a clock cycle tCLK) of an external clock is relatively low, as shown in the timing chart, a clock that lags behind an external clock EXCLK (portion (a) of FIG. 2A) by a given phase (for example, 120.degree.) is used as an internal clock of the semiconductor device. The phase of a DLL clock DLLCLK (portion (c) of FIG. 2A) is compared with the phase of a real clock RECLK (portion (b) of FIG. 2A) within a window that is a cycle of a window pulse signal (hatched portions of FIG. 2A). The window pulse signal is produced by using a division technique of the frequency for the real clock. More particularly, edges (dlos0z and dlos1z) of the clocks occurring within the window are detected and compared with each other. A delay occurring on a clock signal line is included in the delay time td equivalent to a phase delay of the real clock. On the other hand, the DLL clock is leading in anticipation of the delay time td' that may occur in an output circuit, such as the output buffer (as the delay time td' becomes long, the value in which the phase of the DLL clock is leading in comparison with the phase of the real clock increases). The clock phase comparing circuit 150 compares the leading edges (indicated with arrows in the drawing) of the real clock with the leading edges (indicated with arrows in the drawing) of the DLL clock occurring within the window that is the cycle of the window pulse signal. Either one of these two clocks whose leading edge comes earlier than the leading edge of the other clock is detected. In this case (FIG. 2A), the phase of the DLL clock is therefore judged to be leading relative to the phase of the real clock. The DLL clock DLLCLK is output from the clock phase comparing circuit 150. On the other hand, when the leading edge of the real clock comes earlier than the leading edge of the DLL clock, the phase of the real clock is judged to be leading relative to the phase of the DLL clock. The real clock RECLK is output from the clock phase comparing circuit 150. Incidentally, signals dlos0z and dlos1z (corresponding to output signals Sa and Sb, respectively, that will be described later with reference to FIG. 13) are signals produced on the basis of the real clock and of the DLL clock, respectively, for phase comparison (See portions (d) and (e) of FIG. 2A).
As mentioned above, assuming that the clock frequency of an external clock supplied to a semiconductor device is relatively low, and a clock that lags by 90.degree. or 120.degree. is used as a DLL clock, in this case, the phase of a DLL clock produced by a DLL circuit has conventionally been compared with the phase of a real clock that is input to a DRAM. Either one of the above two clocks whose timing comes earlier than the timing of the other clock has been detected and used as an internal clock of the semiconductor device according to the prior art. This is intended to prevent clock access time tAC becoming unnecessarily long.
To be more specific, the DLL circuit adjusts the phase of an internal clock so that a signal will be output from the DRAM synchronously with a clock employed in a computer system. Transmission of a signal within a semiconductor chip is accompanied by a delay. Therefore, the phase of a clock generated by the DLL circuit leads relative to a clock produced outside the semiconductor chip. Actually, the clock generated by the DLL circuit that is leading is produced synchronously with an edge of a given clock of the semiconductor chip which is delayed by the amount of delay corresponding to several cycles of the clock of the semiconductor chip.
Assuming that the clock frequency of an external clock EXCLK (portion (f) of FIG. 2B) shown in a timing chart of FIG. 2B is relatively high, in this case, the phase of a DLL clock DLLCLK (portion (h) of FIG. 2B) is compared with the phase of a real clock (portion (g) of FIG. 2B) within a window that is a cycle of a window pulse signal (hatched portion in the drawing). However, in this condition, the DLL clock tends to deviate from the window by a half cycle. The comparison between the phase of one clock and the phase of another clock may result in a misjudgment that a clock that is leading is regarded as a clock that is lagging.
Specifically, according to the timing chart of FIG. 2B, the clock frequency of an external clock is relatively high and the clock cycle tCLK of the external clock is relatively short in comparison with a delay occurring in a semiconductor device. A leading edge of a DLL clock which is to be compared with a real clock (edge indicated with an arrow in the drawing) rises outside the window. Consequently, although a DLL clock is actually leading relative to a real clock, the DLL clock is judged to lag behind the real clock. As a result, the clock phase comparing circuit does not output the DLL clock DLLCLK (portion (h) of FIG. 2B) that is relatively leading, and outputs a real clock RECLK (portion (g) of FIG. 2B) that is relatively lagging. Thus, a correct judgment is not carried out. Incidentally, signals dlos0z and dlos1z (corresponding to output signals Sa and Sb, respectively, that will be described later with reference to FIG. 13) shown in portions (i) and (j) of FIG. 2B are signals produced on the basis of the real clock and the DLL clock, respectively, for phase comparison.